1. Technical Field
The invention relates to a cell layout arrangement. In particular, the invention relates to a cell layout arrangement with a filler cell for an integrated circuit chip.
2. Background Information
In cell based integrated circuit chips such as application specific integrated circuits (ASICs), FPGA and system-on-chip (SoC) designs, filler cells are used to provide separation between certain types of circuits and voltage biasing cells. In an SoC design, components traditionally manufactured as separate chips to be wired together on a printed circuit board are designed to occupy a single chip that contains memory, microprocessor(s), peripheral interfaces, input/output (I/O) logic control, data converters, and other components that together compose the whole electronic system. One stage during the design of such IC's is “Place and Route”. During the ‘Place and Route’ stage a placement tool optimizes the location of circuits on a die to meet the timing requirements set by the product designer while conforming to placement restrictions to satisfy requirements of the technology, as well as legal placement locations. The placement tool places the circuits optimally to provide adequate space for wiring while the routing tool provides an electrically correct and uncongested distribution of interconnect wiring while meeting the timing requirements. Design Rule Checking (DRC) is carried out during system design to determine whether a particular chip design satisfies a series of recommended parameters called “Design Rules.” Design Rules are a series of parameters provided by semiconductor manufacturers that enable a designer to verify the correctness of the system design. The rules are specific to a particular semiconductor manufacturing process and a design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes so as to ensure most of the parts work correctly.
The filler cells are normally “empty” (i.e. devoid of active devices) and are used not only to avoid DRC violations during ‘Place and Route’ but also to reduce routing congestion. They may contain metal layers up to the M2 layer only. However, the “empty” layout is often inlaid with local capacitors, normally n-channel or p-channel devices configured as two terminal devices, that act as energy wells and minimize supply bounce due to switching activity, especially in high frequency applications.
When used for these purposes, the capacitor of a filler cell must satisfy the following requirements: electrostatic discharge (ESD) and Gate Oxide Integrity (GOI) robustness; minimum usage of routing resources to connect the capacitor device; layout compactness to fit the capacitor device within predefined dimensions; minimal series resistance for use in HF applications; reasonable capacitance per square micron (μm2); and no extra processing mask.
Several variants of such buffer capacitors that meet all or some of the conditions listed above have been proposed and implemented, for example: N-channel (p-channel) gate capacitance but this fails condition 1 and 2; or well diode capacitance but this fails conditions 4 and 5.
In addition to the foregoing, the shrinking gate oxide thickness now occurring as a result of advancing technology prevents direct connection of the gate to the VDD and/or VSS power rails owing to ESD considerations.